During the past forty years, microelectronic technology has been able to shrink the dimensions of its basic element, namely the transistor, and thus to increase the density of transistors in circuits, as well as to improve the performance of each transistor. This increase is found to follow a very well known exponential curve called “Moore's law.” For the first part of this curve, the performance increase was directly derived from the smaller dimensions of the transistor, but for the last ten years, high-performance silicon-based Complementary Metal-Oxide Semiconductor (CMOS) technology has relied heavily on material innovations at the transistor level to maintain generational performance trends.
One aspect of the material innovations was to increase the strain in the silicon crystal to boost carrier mobility and thus to reach high current density, which directly transfers into higher performance for the circuit. This aspect has been pushed to its limits for the last generation of improvements, so now it is either inconceivable to continue to build more strain or the mobility increase saturates even if more strain is applied. Despite this limitation, the need to gain more performance through carrier mobility gain remains.
Field-effect type transistors (FETs) rely on an electric field to control the shape and, hence, the conductivity of a channel of one type of charge carrier in a semiconductor material. While silicon has typically been used in the channels of such transistors, new higher-mobility materials are expected to replace silicon. The most studied high mobility materials for N Field-Effect Transistors (NFETs) are III/V materials, and in particular GaAs and InGaAs. Pure Ge or SiGe alloys are usually contemplated for P Field-Effect Transistors (PFETs). Manufacturing structures comprising such new materials, and in particular Semiconductor-On-Insulator (SeOI) structures, however, remains problematic.
SeOI structures comprise one or more thin layers of semiconductor materials on a buried insulating layer, covering a support substrate, generally made of silicon. But, silicon, on the first hand, and GaAs or InGaAs, on the other hand, are crystalline materials having very different lattice parameters which do not easily match. A layer of InGaAs grown on a silicon substrate therefore presents crystal defects, misfits and dislocations which drastically reduce performances, unless a very thick buffer layer is grown from a silicon substrate to accommodate the large difference in lattice parameter. The growing of such a thick layer is both time consuming and expensive.
Alternatively, support substrates that are more compatible, for example, made of GaAs or InP, do exist, but these alternative substrates are expensive and are available only in limited diameters (e.g., a maximum of 150 mm InP wafers compared with 300 mm silicon wafers). All of these solutions are, therefore, not useful for the manufacture of high-yield microelectronic devices.
Moreover, moving away from silicon to high-mobility materials implies that two different SeOI structures would be required for N or P FETs, whereas silicon is useful for either one.
Finally, there is another major obstacle to form a conventional III/V transistor with implanted source and drain. Indeed, a transistor needs three electrodes, two of then being connection points with the semiconductor material in a FET (at the source and the drain). But, due to doping implantation defects that are impossible to heal, metallic contacts with III/V materials present a high resistance, which also reduces performance.
There is consequently a need for SeOI structures that enable high-yield manufacturing of a III/V high-mobility channel transistors, with low access resistance source and drain contacts, as well as methods of making such structures. These are now provided by the present invention.